1. Field of the Invention
The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same. More specifically, the present invention relates to a bit line barrier metal layer for a semiconductor device, having improved performance and characteristics due to reduction of contact resistance of bit lines and reduction of parasitic capacitance generation between adjacent bit lines, and a process for preparing the same.
2. Description of the Related Art
Recently, with the extremely increased degree of integration of semiconductor devices, materials for bit lines are changing from polysilicon and tungsten silicide structures to chemically vapor deposited tungsten (CVD-W).
As such, in order to form tungsten bit lines, a barrier metal layer should be first vapor-deposited to decrease contact resistance between the tungsten bit lines and a substrate prior to vapor-deposition of tungsten.
For the barrier metal, Ionized Metal Plasma (IMP) Ti—TiN is generally used.
The conventional process for forming bit lines will here be described in more detail.
The process for forming bit lines using the conventional arts involves, firstly forming bit line contact of exposing a part of a substrate on an insulation layer vapor-deposited on the substrate, and then implanting additional ions corresponding to a type of cell transistor onto the exposed substrate. Implantation of additional ions onto the exposed substrate serves to prevent the concentration of ions which were implanted onto the substrate from being decreased in the exposed substrate region, by diffusion of ions through other thermal treatment processes prior to formation of bit lines. When ion concentration of the exposed substrate region, that is, ion concentration of the substrate facing bit lines is lowered, this may result in increased contact resistance therebetween.
Next, IMP Ti is vapor-deposited to a predetermined thickness on the inner wall of the bit line contact under the condition in which bias is not applied, and then the IMP TiN is vapor-deposited thereon by applying a bias of 200 W.
Next, rapid thermal treatment is performed to prepare titanium silicide (TiSix) and then the IMP TiN is vapor-deposited again.
The reason why vapor-deposition of TiN is separately performed in two steps is to correct cracking occurring after rapid thermal treatment, because TiN vapor deposited on the upper part may react with TiSix and Ti of the lower part to produce high-resistance TiF, by way of WF6 gas used for vapor-deposition of tungsten bit lines which will be subsequently formed through columnar grain boundaries.
FIG. 1 is an electron micrograph showing the columnar grain boundary of TiN.
The total thickness of the barrier metal layer is about 500 Å. Where the barrier metal is vapor-deposited to an excessive thickness, an etch amount of the tungsten bit lines is then increased and the height of the tungsten bit lines is likewise increased, thus leading to the occurrence of parasitic capacitance between adjacent tungsten bit lines.
Therefore, the parasitic capacitance, having thus occurred, may cause problems such as decreased capacitance of cell capacitors in semiconductor devices and thus reduction in refresh time.
FIG. 2 schematically shows a position of parasitic capacitance occurring between conventional tungsten bit lines.
As discussed above, in a tungsten bit line manufacturing process of the conventional semiconductor devices utilizing the IMP TiN as the barrier metal, prevention of TiF production caused by penetration of WF6 gas through grain boundaries due to a micro columnar grain structure of the IMP TiN is an important parameter to reduce contact resistance.
However, the above-mentioned IMP TiN columnar grain boundaries suffer from another problem in that a dopant may be diffused to the outside through the columnar grain boundaries.
Conventional DRAM (Dynamic Random Access Memory) employs a PMOS as a cell transistor and the PMOS uses boron (B) ions, which rapidly diffuse into Source and Drain regions, as the dopant.
Since the boron ion dopant exhibits rapid diffusion and thus diffuses through the IMP TiN columnar grain boundaries during a high temperature thermal treatment process, this causes the problem of increasing contact resistance with the bit lines.
In particular, due to the high degree integration of semiconductor devices, when TiN is applied to the semiconductor device of sub-nanometer size, it may cause degradation of the semiconductor device characteristics thus resulting in reduced yield thereof.